Inter-integrated circuit (I2C) interface RM0033
628/1381 RM0033 Rev 9
23.6.9 I
2
C TRISE register (I2C_TRISE)
Address offset: 0x20
Reset value: 0x0002
151413121110987 654321 0
Reserved
TRISE[5:0]
rw rw rw rw rw rw
Bits 15:6 Reserved, must be kept at reset value
Bits 5:0 TRISE[5:0]: Maximum rise time in Fm/Sm mode (Master mode)
These bits should provide the maximum duration of the SCL feedback loop in master mode.
The purpose is to keep a stable SCL frequency whatever the SCL rising edge duration.
These bits must be programmed with the maximum SCL rise time given in the I
2
C bus
specification, incremented by 1.
For instance: in Sm mode, the maximum allowed SCL rise time is 1000 ns.
If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 0x08 and T
PCLK1
= 125 ns
therefore the TRISE[5:0] bits must be programmed with 09h.
(1000 ns / 125 ns = 8 + 1)
The filter value can also be added to TRISE[5:0].
If the result is not an integer, TRISE[5:0] must be programmed with the integer part, in order
to respect the t
HIGH
parameter.
Note: TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).
To Next Page
Loading...
Need help?
General
