ST STM32F207 series - Figure 81. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0 X36; Figure 82. Counter Timing Diagram, Internal Clock Divided by N

Advanced-control timers (TIM1 and TIM8) RM0033
316/1381 RM0033 Rev 9
Figure 81. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
Figure 82. Counter timing diagram, internal clock divided by N
0034 0035
MS31191V2
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag (UIF)
CNT_EN
0036 0035
MS31192V2
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Update interrupt flag (UIF)
Counter underflow
001F20 01