Cryptographic processor (CRYP) RM0033
508/1381 RM0033 Rev 9
19 Cryptographic processor (CRYP)
This section applies to the whole STM32F20x and STM32F21x family, unless otherwise
specified.
19.1 CRYP introduction
The cryptographic processor can be used to both encipher and decipher data using the
DES, Triple-DES or AES (128, 192, or 256) algorithms. It is a fully compliant implementation
of the following standards:
• The data encryption standard (DES) and Triple-DES (TDES) as defined by Federal
Information Processing Standards Publication (FIPS PUB 46-3, 1999 October 25). It
follows the American National Standards Institute (ANSI) X9.52 standard.
• The advanced encryption standard (AES) as defined by Federal Information
Processing Standards Publication (FIPS PUB 197, 2001 November 26)
The CRYP processor performs data encryption and decryption using DES and TDES
algorithms in Electronic codebook (ECB) or Cipher block chaining (CBC) mode.
The CRYP peripheral is a 32-bit AHB2 peripheral. It supports DMA transfer for incoming and
processed data, and has input and output FIFOs (each 8 words deep).
19.2 CRYP main features
• Suitable for AES, DES and TDES enciphering and deciphering operations
• AES
– Supports the ECB, CBC, CTR chaining algorithms
– Supports 128-, 192- and 256-bit keys
– 4 × 32-bit initialization vectors (IV) used in the CBC, CTR modes
Table 73. Number of cycles required to process each 128-bit block
Algorithm / Key size ECB CBC CTR
128b 14 14 14
192b 16 16 16
256b 18 18 18
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