Flexible static memory controller (FSMC) RM0033
1286/1381 RM0033 Rev 9
If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access
phase (Data setup phase) programmed by the DATAST bits, is extended until WAIT
becomes inactive. Unlike the data setup phase, the first access phases (Address setup and
Address hold phases), programmed by the ADDSET[3:0] and ADDHLD bits, are not WAIT
sensitive and so they are not prolonged.
The data setup phase (DATAST in the FSMC_BTRx register) must be programmed so that
WAIT can be detected 4 HCLK cycles before the end of memory transaction. The following
cases must be considered:
1. DATAST in FSMC_BTRx register) Memory asserts the WAIT signal aligned to
NOE/NWE which toggles:
2. Memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
if
then
otherwise
where max_wait_assertion_time is the maximum time taken by the memory to assert
the WAIT signal once NEx/NOE/NWE is low.
Figure 412 and Figure 413 show the number of HCLK clock cycles that are added to the
memory access after WAIT is released by the asynchronous memory (independently of the
above cases).
DATAST 4 HCLK×()max_wait_assertion_time+≥
max_wait_assertion_time address_phase hold_phase+>
DATAST 4 HCLK×()max_wait_assertion_time address_phase– hold_phase–()+≥
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