RM0033 Rev 9 1353/1381
RM0033 Revision history
1375
09-Dec-2010
2
(continued)
DAC
Updated V
REF
range in Table 41: DAC pins.
Camera interface (DCMI)
Recommended 32-bit access for DCMI registers.
Removed F
PIXCLK
maximum value in Section 12.4: DCMI clocks.
Section 12.5: DCMI functional overview; updated Figure 57 to
remove NRST
, AHB, DMA_ACK, and change IT_CCI to DCMI_IT.
Removed section “Slave AHB interface”.
Updated Section 12.5.1: DMA interface overview and removed figure
DMA transfer.
Changed clock to pixel clock in Section 12.5.2: DCMI physical
interface, and Figure 58 corrected.
Removed section “Parallel interface width”.
Section 12.8.1: DCMI control register 1 (DCMI_CR): removed CRE
bit, updated ESS bit description to distinguish between hardware and
embedded synchronization, replaced RAM by destination memory in
CM and CAPTURE bit description. Added note for ERR_IE and
ERR_ISC.
Section 12.8.3: DCMI raw interrupt status register
(DCMI_RIS)/Section 12.8.5: DCMI masked interrupt status register
(DCMI_MIS): added note to indicated that ERR_RIS/MIS bit is
available only in embedded synchronization mode.
Added note for ERR_IE and ERR_ISC in Section 12.8.4: DCMI
interrupt enable register (DCMI_IER).
All OVR_ bit descriptions changed to overrun status.
General-purpose timers (TIM9 to TIM14)
Updated CC1NP and CC2NP for
TIM9/12 in Section 15.3.5: Input
capture mode, Section 15.3.6: PWM input mode (only for TIM9/12),
Section 15.3.10: One-pulse mode.
Updated URS and UDIS bit description in Section 15.4.1: TIM9/12
control register 1 (TIMx_CR1).
Updated description of CC1IF and UIF bits in Section 15.4.5:
TIM9/12 status register (TIMx_SR).
Updated description of TG and UG bits in Section 15.4.6: TIM9/12
event generation register (TIMx_EGR).
Added CC1NP and CC2NP bits in Section 15.4.8: TIM9/12
capture/compare enable register (TIMx_CCER).
Updated UDIS, URS, and CEN bit description in Section 15.4.1:
TIM9/12 control register 1 (TIMx_CR1). Removed TIM10/11/13/14
TIMx_CR2 register.
Updated CC1IF and UIF bit description in Section 15.5.3:
TIM10/11/13/14 status register (TIMx_SR).
Updated UG bit description in Section 15.5.4: TIM10/11/13/14 event
generation register (TIMx_EGR).
Updated OC1M and OC1PE bit description; and changed bit 2
register from reserved to OC1FE in Section 15.5.5: TIM10/11/13/14
capture/compare mode register 1 (TIMx_CCMR1).
Table 224. Document revision history (continued)
Date Version Changes
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