Revision history RM0033
1354/1381 RM0033 Rev 9
09-Dec-2010
2
(continued)
General-purpose timers (TIM9 to TIM14) (continued)
Added OC1FE bit and updated CC1NP bit description in
Section 15.5.6: TIM10/11/13/14 capture/compare enable register
(TIMx_CCER).
Updated TI1_RMP bit description in Section 15.5.12:
TIM10/11/13/14 register map.
Real-time clock (RTC)Section 22: Real-time clock (RTC)
Whole Section 22: Real-time clock (RTC) reworked without major
content update.
Renamed TAMPER pin to TAMPER1, and AFI_TAMPER to
AFI_TAMPER1.
Renamed TAMPF to TAMP1F in Section 22.6.4: RTC initialization
and status register (RTC_ISR).
Renamed TAMPINSEL to TAMP1INSEL, TAMPE to TAMP1E, and
TAMPEDGE to TAMP1TRG in Section 22.6.13: RTC tamper and
alternate function configuration register (RTC_TAFCR),
I2C
Updated last two steps of the closing communication sequence in
Section : Master receiver.
Removed EV6_1 in Figure 219: Transfer sequence diagram for slave
receiver.
USART
Modified Section : LIN reception.
Updated Table 97: USART mode configuration to add DMA support
for UART5.
SPI
Updated Table 100: Audio frequency precision (for PLLM VCO =
1 MHz or 2 MHz) title to add 2 MHz PLL inputs frequency.
Updated Figure 280: PCM standard waveforms (16-bit).
CAN:
Update description of LEC bits in Section : CAN error status register
(CAN_ESR).
Ethernet
Removed ETH _RMII_TX_CLK alternated function for PC3 in
Table 138: Alternate function mapping.
Changed FIFO size in Figure 313: ETH block diagram.
Removed restriction related to PTP frame identification in Section :
Reception of frames with the PTP feature.
Removed time-stamp low/high[31:0] in Figure 343: Enhanced
transmit descriptor.
Removed sections “Tx/RxDMA descriptor format with IEEE1588 time
stamp".
Table 224. Document revision history (continued)
Date Version Changes