USB on-the-go high-speed (OTG_HS) RM0033
1148/1381 RM0033 Rev 9
313029282726252423222120191817161514131211109876543210
Reserved
FSLSS
FSLSPCS
rrwrw
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 FSLSS: FS- and LS-only support
The application uses this bit to control the core’s enumeration speed. Using this bit, the
application can make the core enumerate as an FS host, even if the connected device
supports HS traffic. Do not make changes to this field after initial programming.
0: HS/FS/LS, based on the maximum speed supported by the connected device
1: FS/LS-only, even if the connected device can support HS (read-only)
Bits 1:0 FSLSPCS: FS/LS PHY clock select
When the core is in FS host mode:
01: PHY clock is running at 48 MHz
Others: Reserved
When the core is in LS host mode:
00: Reserved
01: PHY clock is running at 48 MHz.
10: Select 6 MHz PHY clock frequency
11: Reserved
Note: The FSLSPCS bit must be set on a connection event according to the speed of the
connected device. A software reset must be performed after changing this bit.
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