RM0033 Rev 9 1229/1381
RM0033 USB on-the-go high-speed (OTG_HS)
1260
c) The OTG_HS host starts writing the received data to the system memory as soon
as the last byte is received with no errors.
d) When the last packet is received, the OTG_HS host sets an internal flag to remove
any extra IN requests from the request queue.
e) The OTG_HS host flushes the extra requests.
f) The final request to disable channel x is written to the request queue. At this point,
channel 2 is internally masked for further arbitration.
g) The OTG_HS host generates the CHH interrupt as soon as the disable request
comes to the top of the queue.
h) In response to the CHH interrupt, de-allocate the channel for other transfers.
• Interrupt OUT transactions in DMA mode
a) Initialize and enable channel x as explained in Section : Channel initialization.
b) The OTG_HS host starts fetching the first packet as soon the channel is enabled
and writes the OUT request along with the last word fetch. In high-bandwidth
transfers, the HS_OTG host continues fetching the next packet (up to the value
specified in the MC field) before switching to the next channel.
c) The OTG_HS host attempts to send the OUT token at the beginning of the next
odd frame/micro-frame.
d) After successfully transmitting the packet, the OTG_HS host generates a CHH
interrupt.
e) In response to the CHH interrupt, reinitialize the channel for the next transfer.
• Interrupt IN transactions in DMA mode
The sequence of operations (channelx) is as follows:
a) Initialize and enable channel x as explained in Section : Channel initialization.
b) The OTG_HS host writes an IN request to the request queue as soon as the
channel x gets the grant from the arbiter (round-robin with fairness). In high-
bandwidth transfers, the OTG_HS host writes consecutive writes up to MC times.
c) The OTG_HS host attempts to send an IN token at the beginning of the next (odd)
frame/micro-frame.
d) As soon the packet is received and written to the receive FIFO, the OTG_HS host
generates a CHH interrupt.
e) In response to the CHH interrupt, reinitialize the channel for the next transfer.
• Isochronous OUT transactions in DMA mode
a) Initialize and enable channel x as explained in Section : Channel initialization.
b) The OTG_HS host starts fetching the first packet as soon as the channel is
enabled, and writes the OUT request along with the last word fetch. In high-
bandwidth transfers, the OTG_HS host continues fetching the next packet (up to
the value specified in the MC field) before switching to the next channel.
c) The OTG_HS host attempts to send an OUT token at the beginning of the next
(odd) frame/micro-frame.
d) After successfully transmitting the packet, the HS_OTG host generates a CHH
interrupt.
e) In response to the CHH interrupt, reinitialize the channel for the next transfer.
• Isochronous IN transactions in DMA mode
The sequence of operations ((channel x) is as follows:
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