RM0033 Rev 9 1239/1381
RM0033 USB on-the-go high-speed (OTG_HS)
1260
Application programming sequence:
1. To stop receiving any kind of data in the receive FIFO, the application must set the
Global OUT NAK bit by programming the following field:
– SGONAK = 1 in OTG_HS_DCTL
2. Wait for the assertion of the GONAKEFF interrupt in OTG_HS_GINTSTS. When
asserted, this interrupt indicates that the core has stopped receiving any type of data
except SETUP packets.
3. The application can receive valid OUT packets after it has set SGONAK in
OTG_HS_DCTL and before the core asserts the GONAKEFF interrupt
(OTG_HS_GINTSTS).
4. The application can temporarily mask this interrupt by writing to the GINAKEFFM bit in
GINTMSK.
– GINAKEFFM = 0 in GINTMSK
5. Whenever the application is ready to exit the Global OUT NAK mode, it must clear the
SGONAK bit in OTG_HS_DCTL. This also clears the GONAKEFF interrupt
(OTG_HS_GINTSTS).
– OTG_HS_DCTL = 1 in CGONAK
6. If the application has masked this interrupt earlier, it must be unmasked as follows:
– GINAKEFFM = 1 in GINTMSK
• Disabling an OUT endpoint
The application must use this sequence to disable an OUT endpoint that it has enabled.
Application programming sequence:
1. Before disabling any OUT endpoint, the application must enable Global OUT NAK
mode in the core.
– SGONAK = 1 in OTG_HS_DCTL
2. Wait for the GONAKEFF interrupt (OTG_HS_GINTSTS)
3. Disable the required OUT endpoint by programming the following fields:
– EPDIS = 1 in OTG_HS_DOEPCTLx
– SNAK = 1 in OTG_HS_DOEPCTLx
4. Wait for the EPDISD interrupt (OTG_HS_DOEPINTx), which indicates that the OUT
endpoint is completely disabled. When the EPDISD interrupt is asserted, the core also
clears the following bits:
– EPDIS = 0 in OTG_HS_DOEPCTLx
– EPENA = 0 in OTG_HS_DOEPCTLx
5. The application must clear the Global OUT NAK bit to start receiving data from other
nondisabled OUT endpoints.
– SGONAK = 0 in OTG_HS_DCTL
• Transfer Stop Programming for OUT endpoints
The application must use the following programing sequence to stop any transfers (because
of an interrupt from the host, typically a reset).
Sequence of operations:
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