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ST STM32F207 series User Manual

ST STM32F207 series
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RM0033 Rev 9 1243/1381
RM0033 USB on-the-go high-speed (OTG_HS)
1260
1. Program the OTG_HS_DOEPTSIZx register for the transfer size and the
corresponding packet count
2. Program the OTG_HS_DOEPCTLx register with the endpoint characteristics and set
the Endpoint Enable, ClearNAK, and Even/Odd frame bits.
EPENA = 1
–CNAK=1
EONUM = (0: Even/1: Odd)
3. In Slave mode, wait for the RXFLVL interrupt (in OTG_HS_GINTSTS) and empty the
data packets from the receive FIFO
This step can be repeated many times, depending on the transfer size.
4. The assertion of the XFRC interrupt (in OTG_HS_DOEPINTx) marks the completion of
the isochronous OUT data transfer. This interrupt does not necessarily mean that the
data in memory are good.
5. This interrupt cannot always be detected for isochronous OUT transfers. Instead, the
application can detect the IISOOXFRM interrupt in OTG_HS_GINTSTS.
6. Read the OTG_HS_DOEPTSIZx register to determine the size of the received transfer
and to determine the validity of the data received in the frame. The application must
treat the data received in memory as valid only if one of the following conditions is met:
RXDPID = D0 (in OTG_HS_DOEPTSIZx) and the number of USB packets in
which this payload was received = 1
RXDPID = D1 (in OTG_HS_DOEPTSIZx) and the number of USB packets in
which this payload was received = 2
RXDPID = D2 (in OTG_HS_DOEPTSIZx) and the number of USB packets in
which this payload was received = 3
The number of USB packets in which this payload was received =
Application programmed initial packet count – Core updated final packet count
The application can discard invalid data packets.
Incomplete isochronous OUT data transfers
This section describes the application programming sequence when isochronous OUT data
packets are dropped inside the core.
Internal data flow:
1. For isochronous OUT endpoints, the XFRC interrupt (in OTG_HS_DOEPINTx) may not
always be asserted. If the core drops isochronous OUT data packets, the application
could fail to detect the XFRC interrupt (OTG_HS_DOEPINTx) under the following
circumstances:
When the receive FIFO cannot accommodate the complete ISO OUT data packet,
the core drops the received ISO OUT data
When the isochronous OUT data packet is received with CRC errors
When the isochronous OUT token received by the core is corrupted
When the application is very slow in reading the data from the receive FIFO
2. When the core detects an end of periodic frame before transfer completion to all
isochronous OUT endpoints, it asserts the incomplete Isochronous OUT data interrupt
(IISOOXFRM in OTG_HS_GINTSTS), indicating that an XFRC interrupt (in
OTG_HS_DOEPINTx) is not asserted on at least one of the isochronous OUT
endpoints. At this point, the endpoint with the incomplete transfer remains enabled, but
no active transfers remain in progress on this endpoint on the USB.

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ST STM32F207 series Specifications

General IconGeneral
BrandST
ModelSTM32F207 series
CategoryMicrocontrollers
LanguageEnglish

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