RM0033 Rev 9 695/1381
RM0033 Serial peripheral interface (SPI)
734
pin. The software must have written the data to be sent before the SPI master
device initiates the transfer.
• In unidirectional receive-only mode (BIDIMODE=0 and RXONLY=1)
– The sequence begins when the slave device receives the clock signal and the first
bit of the data on its MOSI pin. The 7 remaining bits are loaded into the shift
register.
– The transmitter is not activated and no data are shifted out serially to the MISO
pin.
• In bidirectional mode, when transmitting (BIDIMODE=1 and BIDIOE=1)
– The sequence begins when the slave device receives the clock signal and the first
bit in the Tx buffer is transmitted on the MISO pin.
– The data are then parallel loaded from the Tx buffer into the 8-bit shift register
during the first bit transmission and then shifted out serially to the MISO pin. The
software must have written the data to be sent before the SPI master device
initiates the transfer.
– No data are received.
• In bidirectional mode, when receiving (BIDIMODE=1 and BIDIOE=0)
– The sequence begins when the slave device receives the clock signal and the first
bit of the data on its MISO pin.
– The received data on the MISO pin are shifted in serially to the 8-bit shift register
and then parallel loaded into the SPI_DR register (Rx buffer).
– The transmitter is not activated and no data are shifted out serially to the MISO
pin.
Handling data transmission and reception
The TXE flag (Tx buffer empty) is set when the data are transferred from the Tx buffer to the
shift register. It indicates that the internal Tx buffer is ready to be loaded with the next data.
An interrupt can be generated if the TXEIE bit in the SPI_CR2 register is set. Clearing the
TXE bit is performed by writing to the SPI_DR register.
Note: The software must ensure that the TXE flag is set to 1 before attempting to write to the Tx
buffer. Otherwise, it overwrites the data previously written to the Tx buffer.
The RXNE flag (Rx buffer not empty) is set on the last sampling clock edge, when the data
are transferred from the shift register to the Rx buffer. It indicates that data are ready to be
read from the SPI_DR register. An interrupt can be generated if the RXNEIE bit in the
SPI_CR2 register is set. Clearing the RXNE bit is performed by reading the SPI_DR
register.
For some configurations, the BSY flag can be used during the last data transfer to wait until
the completion of the transfer.
Full-duplex transmit and receive procedure in master or slave mode (BIDIMODE=0 and
RXONLY=0)
The software has to follow this procedure to transmit and receive data (see Figure 255 and
Figure 256):
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