ST STM32F207 series User Manual

RM0033 Rev 9 1183/1381
RM0033 USB on-the-go high-speed (OTG_HS)
1260
OTG_HS device endpoint-x interrupt register (OTG_HS_DOEPINTx) (x = 0..5,
where x = Endpoint_number)
Address offset: 0xB08 + 0x20 * x
Reset value: 0x0000 0080
This register indicates the status of an endpoint with respect to USB- and AHB-related
events. It is shown in Figure 377. The application must read this register when the OUT
Endpoints Interrupt bit of the Core interrupt register (OEPINT bit in OTG_HS_GINTSTS) is
set. Before the application can read this register, it must first read the device all endpoints
interrupt (OTG_HS_DAINT) register to get the exact endpoint number for the device
Endpoint-x interrupt register. The application must clear the appropriate bit in this register to
clear the corresponding bits in the OTG_HS_DAINT and OTG_HS_GINTSTS registers.
313029282726252423222120191817161514131211109876543210
Reserved
NYET
NAK
BERR
Reserved
OUTPKTERR
Reserved
B2BSTUP
Reserved
OTEPDIS
STUP
AHBERR
EPDISD
XFRC
rc_
w1
rc_
w1
rc_
w1
rc_
w1
rc_
w1
rc_
w1
rc_
w1
rc_
w1
rc_
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rc_
w1
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 NYET: NYET interrupt
The core generates this interrupt when a NYET response is transmitted for a
nonisochronous OUT endpoint.
Bit 13 NAK: NAK input
The core generates this interrupt when a NAK is transmitted or received by the device. In
case of isochronous IN endpoints the interrupt gets generated when a zero length packet is
transmitted due to unavailability of data in the Tx FIFO.
Bit 12 BERR: Babble error interrupt
The core generates this interrupt when babble is received for the endpoint.
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 OUTPKTERR: OUT packet error
This interrupt is asserted when the core detects an overflow or a CRC error for an OUT
packet. This interrupt is valid only when thresholding is enabled.
Bit 7 Reserved, must be kept at reset value.
Bit 6 B2BSTUP: Back-to-back SETUP packets received
Applies to Control OUT endpoint only.
This bit indicates that the core has received more than three back-to-back SETUP packets
for this particular endpoint.
Bit 5 Reserved, must be kept at reset value.
Bit 4 OTEPDIS: OUT token received when endpoint disabled
Applies only to control OUT endpoint.
Indicates that an OUT token was received when the endpoint was not yet enabled. This
interrupt is asserted on the endpoint for which the OUT token was received.

ST STM32F207 series Specifications

General

Brand	ST
Model	STM32F207 series
Category	Microcontrollers
Language	English