Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Functional group
See 5.2 Distributor registers (GICD/GICDA) summary on page 98 for the address offset,
type, and reset value of this register.
Usage constraints
Some bits are only accessible by Secure accesses.
Bit descriptions
Figure 5-4: GICD_FCTLR bit assignments
31 4 3 1 0
CGO
29 19 18 17 16 15
Reserved
NSACR
Reserved SIP
Reserved
DCC
28 27 26 25 24 22 21 20 14 13
QDENY
POS
Reserved
ReservedReservedReserved
Table 5-6: GICD_FCTLR bit descriptions
Bits Name Description
[31:29] - Reserved, returns 0b00000
[28:27] - Reserved, RES0
[26] POS Point of serialization. When an interrupt is sent remotely and POS is set, it ensures that writes to GICD_SETSPI and
GICD_CLRSPI propagate to remote chips before ACE-Lite sends a response. Applies only to edge-triggered interrupts.
0 Store locally and propagate when possible
1 Propagate access to POS
Resets to 0b0.
[25] QDENY Q-Channel deny. Overrides the Q-Channel logic and forces the Distributor to reject powerdown requests.
[24:22] - Reserved, RES0
[21] DCC Do not correct cache. Modifies the a<x>cache output signals from the Distributor. See 4.11 Memory access and
attributes on page 64.
[20:19] - Reserved, RES0
[18] - Reserved
[17:16] NSACR Non-secure access control. Values are as described in the GICD_NSACR register. This is the value that is used if an SPI
has an error.
Secure access only.
Resets to 0b00.
[15:14] - Reserved, returns 0b00
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