Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Contents
6.9 AXI4-Stream internal interconnect protection.................................................................................... 226
6.9.1 GIC-rendered partially duplicated interconnect.............................................................................. 226
6.9.2 Non-GIC interconnect IP...................................................................................................................... 228
6.10 P-Channel and Q-Channel protection................................................................................................232
6.10.1 CHK bit timing......................................................................................................................................235
6.10.2 Transient faults......................................................................................................................................236
6.10.3 Stuck-at faults....................................................................................................................................... 238
6.10.4 Disabling P-Channel and Q-Channel Safety Mechanisms..........................................................239
6.10.5 P-Channel...............................................................................................................................................239
6.10.6 Q-Channel..............................................................................................................................................241
6.11 PPI and SPI interrupt interface protection........................................................................................ 244
6.11.1 PPI and SPI CHK bit timing...............................................................................................................244
6.11.2 PPI and SPI transient faults...............................................................................................................245
6.11.3 PPI and SPI stuck-at faults................................................................................................................ 246
6.11.4 PPI and SPI configuration parameters.............................................................................................246
6.12 Systematic fault watchdog protection................................................................................................246
6.13 DFT protection.........................................................................................................................................247
6.13.1 MBIST..................................................................................................................................................... 247
6.13.2 ATPG/Scan............................................................................................................................................ 248
6.13.3 LBIST....................................................................................................................................................... 248
6.14 Generic fault inputs................................................................................................................................ 248
6.15 Configuration and parameters..............................................................................................................249
A. Signal descriptions.....................................................................................................................................250
A.1 Common control signals...........................................................................................................................250
A.2 Power control signals................................................................................................................................251
A.3 Interrupt signals..........................................................................................................................................253
A.4 CPU interface signals................................................................................................................................254
A.5 ACE-Lite interface signals........................................................................................................................255
A.6 Miscellaneous signals................................................................................................................................258
A.7 Interblock AXI4-Stream interface signals............................................................................................. 260
A.8 Interdomain signals....................................................................................................................................262
A.9 Interchip AXI4-Stream interface signals............................................................................................... 262
B. Implementation-defined features.......................................................................................................... 263
C. Revisions...................................................................................................................................................... 265
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