Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Contents
5.10.11 FMU_STATUS, FMU Status register............................................................................................. 191
5.10.12 FMU_ERRIDR, Error Record ID Register......................................................................................191
6. Functional Safety........................................................................................................................................193
6.1 Safety Mechanism overview................................................................................................................... 193
6.2 Fault Management Unit............................................................................................................................196
6.2.1 FMU APB4 interface............................................................................................................................. 197
6.2.2 Error signaling..........................................................................................................................................197
6.2.3 Error record format................................................................................................................................ 198
6.2.4 FMU reset................................................................................................................................................ 199
6.2.5 Safety Mechanism IDs...........................................................................................................................199
6.2.6 Ping mechanisms.................................................................................................................................... 203
6.2.7 Lock and key mechanism......................................................................................................................206
6.2.8 Correctable Error enable...................................................................................................................... 207
6.2.9 Software interaction...............................................................................................................................207
6.3 FuSa programmer's view.......................................................................................................................... 209
6.4 FuSa I/O.......................................................................................................................................................209
6.4.1 Non-architected FuSa ports.................................................................................................................209
6.4.2 P-Channel and Q-Channel FuSa ports.............................................................................................. 210
6.4.3 AMBA interface FuSa ports................................................................................................................. 211
6.5 Clocks and resets.......................................................................................................................................211
6.5.1 Clocks........................................................................................................................................................ 212
6.5.2 Resets........................................................................................................................................................ 214
6.6 Lock-step protection..................................................................................................................................217
6.6.1 Comparators.............................................................................................................................................218
6.6.2 Non-resettable flops.............................................................................................................................. 219
6.6.3 Reset.......................................................................................................................................................... 219
6.6.4 Error injection..........................................................................................................................................219
6.7 RAM protection.......................................................................................................................................... 219
6.7.1 SECDED ECC data protection............................................................................................................ 220
6.7.2 Address protection................................................................................................................................. 220
6.7.3 RAM scrubbing........................................................................................................................................221
6.8 External interface protection...................................................................................................................221
6.8.1 ACE-Lite interface parity protection..................................................................................................222
6.8.2 AXI4-Stream interface parity protection........................................................................................... 224
6.8.3 APB interface parity protection.......................................................................................................... 225
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