Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Contents
5.8.2 GICT_ERR<n>CTLR, Error Record Control Register.......................................................................150
5.8.3 GICT_ERR<n>STATUS, Error Record Primary Status Register.....................................................151
5.8.4 GICT_ERR<n>ADDR, Error Record Address Register....................................................................152
5.8.5 GICT_ERR<n>MISC0, Error Record Miscellaneous Register 0.................................................... 153
5.8.6 GICT_ERR<n>MISC1, Error Record Miscellaneous Register 1.................................................... 158
5.8.7 GICT_ERRGSR, Error Group Status Register....................................................................................159
5.8.8 GICT_ERRIRQCR<n>, Error Interrupt Configuration Registers....................................................160
5.8.9 GICT_DEVID, Device Configuration register................................................................................... 161
5.8.10 GICT_PIDR2, Peripheral ID2 Register............................................................................................. 162
5.9 GICP register summary.............................................................................................................................163
5.9.1 GICP_EVCNTRn, Event Counter Registers.......................................................................................164
5.9.2 GICP_EVTYPERn, Event Type Configuration Registers................................................................. 164
5.9.3 GICP_SVRn, Shadow Value Registers................................................................................................ 168
5.9.4 GICP_FRn, Filter Registers................................................................................................................... 169
5.9.5 GICP_CNTENSET0, Counter Enable Set Register 0...................................................................... 170
5.9.6 GICP_CNTENCLR0, Counter Enable Clear Register 0.................................................................. 170
5.9.7 GICP_INTENSET0, Interrupt Contribution Enable Set Register 0...............................................171
5.9.8 GICP_INTENCLR0, Interrupt Contribution Enable Clear Register 0...........................................172
5.9.9 GICP_OVSCLR0, Overflow Status Clear Register 0.......................................................................173
5.9.10 GICP_OVSSET0, Overflow Status Set Register 0.........................................................................174
5.9.11 GICP_CAPR, Counter Shadow Value Capture Register.............................................................. 175
5.9.12 GICP_CFGR, Configuration Information Register.........................................................................176
5.9.13 GICP_CR, Control Register................................................................................................................ 176
5.9.14 GICP_IRQCR, Interrupt Configuration Register............................................................................ 177
5.9.15 GICP_PIDR2, Peripheral ID2 Register............................................................................................. 178
5.10 FMU register summary.......................................................................................................................... 179
5.10.1 FMU_ERR<n>FR, Error Record Feature Register......................................................................... 180
5.10.2 FMU_ERR<n>CTLR, Error Record Control Register.................................................................... 181
5.10.3 FMU_ERR<n>STATUS, Error Record Primary Status register....................................................182
5.10.4 FMU_ERRGSR, Error Group Status Register................................................................................. 184
5.10.5 FMU_KEY, FMU Key register............................................................................................................184
5.10.6 FMU_PINGCTLR, Ping Control Register.........................................................................................185
5.10.7 FMU_PINGNOW, Ping Now register.............................................................................................. 186
5.10.8 FMU_SMEN, Safety Mechanism Enable register......................................................................... 187
5.10.9 FMU_SMINJERR, Safety Mechanism Inject Error register......................................................... 189
5.10.10 FMU_PINGMASK, Ping Mask register..........................................................................................190
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