Arm
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CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
About the GIC-600AE
The LPI functionality for all cores on a chip is combined into a single cache in the Distributor.
Redistributor
The Redistributor maintains the Private Peripheral Interrupts (PPIs) and Software Generated
Interrupts (SGIs) for a particular set of cores. A Redistributor can scale from 1-64 cores and is
best placed next to the processors that it is servicing to reduce wiring to the cores.
A Redistributor is also referred to as a PPI block.
The GICv3 architecture specifies a Redistributor address space containing two pages per
core. The SGI page functionality is contained in the GIC-600AE Redistributor. However, the
command and control pages for all cores on a chip are contained in the Distributor.
The GIC-600AE supports powering down the Redistributors and the associated cores.
Interrupt Translation Service
The ITS translates message-based interrupts, Message-Signaled Interrupts (MSI/MSIx), from an
external PCI Express (PCIe) Root Complex (RC), or other sources. The ITS also manages LPIs
during core power management.
The GIC-600AE supports up to eight ITS blocks per chip.
For more information about the ITS, see the GICv3 and GICv4 Software Overview.
MSI-64 Encapsulator
The MSI-64 Encapsulator is a small block that combines the DeviceID (DID), required by
writes to the GITS_TRANSLATER register, into a single memory access.
SPI Collator
The GIC-600AE supports up to 960 SPIs that are spread across the system. The SPI Collator
enables SPIs to be converted into messages remotely from the Distributor. This enables
hierarchical clock gating of the Distributor and the use of other more aggressive low-power
states.
Wake Request
The Wake Request contains all the architecturally defined wake_request signals for each core
on the chip. It is a separate block that can be positioned remotely from the Distributor, such
as next to a system control processor if necessary.
GIC interconnect
The GIC interconnect is a set of components that can be used for routing the AXI4-Stream
interfaces between the different blocks.
Top level
The top level has no specific interfaces but combines the interfaces of other blocks within
the clock or power domain to reduce the number of domain bridges. The GIC-600AE build
scripts enable you to build the GIC from a single combined block or a set of individual blocks
that are interconnected using your own transport layer.
These blocks can be combined in different ways:
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