ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Functional Safety
Figure 6-1: Safety Mechanism distribution
ITS
PCIe
ACE-Lite
Q-Channel
P
P
CRC/parity
ITS
PCIe
P
CRC/parity
Message interrupts
SPI Collator
SPI interrupts
CRC/parity
Distributor
CRC/parity
CRC/parity CRC/parity
P
P
P
FMU
APB
fmu_fault_int
(FHI)
fmu_err_int
(ERI)
P-Channel
Chip2Chip
CRC/parity CRC/parity
ADB
Redistributor
Redistributor
CRC/parity CRC/parity
P P
CPU interface
CPU interface
PPI interrupts
PPI interrupts
Register slice
Legend:
AXI4-Stream interconnect
protection (partial duplication)
Interrupt protection (parity)
Interface protection (AMBA FuSa)
RAM
(SECDED)
Logic
(duplication)
P
Parity protection
AXI4-Stream interconnect
ACE-Lite
AXI4-Stream with protection
GIC-600AE contains the following FuSa Safety Mechanisms.
Lockstep logic protection
The logic is protected with duplicated logic running in lockstep.
RAM protection
The RAMs are shared between the duplicated blocks and are protected with SECDED ECC. The
address is further protected with parity.
AXI4-Stream interconnect protection
The AXI4-Stream interconnect that connects the GIC blocks, is protected by end-to-end
partial duplication. Partial duplication means that the primary interconnect is duplicated with
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