Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Functional Safety
6.10.5.1.1 Capturing pstate signal
In a non-FuSa case, the pstate signal is captured with a synchronized preq signal. In the FuSa case,
we must wait until both the preq and preqchk signals are at the correct level before sampling the
pstate and pstatechk signals. At capture, the pstatechk signal is then tested against the pstate
signal.
The implied timing constraint is similar to the non-FuSa constraint:
Non-FuSa P-Channel constraint
pstate maximum delay < preq signal delay + 2 capture cycles
FuSa P-Channel constraint
•
pstate and pstatechk maximum delay < preq signal delay + 2 capture cycles
•
pstate and pstatechk maximum delay < preqchk signal delay + 2 capture cycles
6.10.5.2 P-Channel acceptance
The following figure shows the opposite polarity of the chk signal bits and the pstatechk signal bit
during the P-Channel acceptance and entry sequence.
Figure 6-21: P-Channel acceptance
PREQ
PACCEPT
State 001
PSTATE[M:0]
PDENY
Power
Controller Actions
Pre-Transition Actions Post-Transition Actions
P_REQUEST P_ACCEPT P_COMPLETEP_STABLE P_STABLE
State 000
PSTATECHK
PREQCHK
PACCEPTCHK
PDENYCHK
t0 t1 t2 t3 t4 t5 t6
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