Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Contents
3.3.5 ITS configuration....................................................................................................................................... 39
3.4 MSI-64 Encapsulator................................................................................................................................... 40
3.4.1 MSI-64 ACE-Lite interfaces................................................................................................................... 40
3.4.2 MSI-64 Encapsulator configuration...................................................................................................... 41
3.5 SPI Collator.................................................................................................................................................... 42
3.5.1 SPI Collator AXI4-Stream interface...................................................................................................... 42
3.5.2 SPI Collator wires......................................................................................................................................42
3.5.3 SPI Collator power Q-Channel.............................................................................................................. 43
3.5.4 SPI Collator clock Q-Channel................................................................................................................ 43
3.5.5 SPI Collator configuration....................................................................................................................... 44
3.6 Wake Request............................................................................................................................................... 44
3.6.1 Wake Request AXI4-Stream interface..................................................................................................45
3.6.2 Wake Request configuration.................................................................................................................. 45
3.7 Interconnect................................................................................................................................................... 45
3.7.1 Interconnect configuration......................................................................................................................46
3.8 Hierarchy.........................................................................................................................................................46
4. Operation........................................................................................................................................................48
4.1 Interrupt types.............................................................................................................................................. 48
4.1.1 SGIs...............................................................................................................................................................48
4.1.2 PPIs............................................................................................................................................................... 48
4.1.3 SPIs............................................................................................................................................................... 49
4.1.4 LPIs............................................................................................................................................................... 49
4.1.5 Choosing between LPIs and SPIs..........................................................................................................50
4.2 Interrupt groups and security....................................................................................................................51
4.3 Physical interrupt signals (PPIs and SPIs)................................................................................................52
4.4 Affinity routing and assignment................................................................................................................53
4.5 SPI routing and 1 of N selection..............................................................................................................54
4.6 Power management..................................................................................................................................... 56
4.6.1 Redistributor power management.........................................................................................................56
4.6.2 Processor core power management..................................................................................................... 57
4.6.3 Other power management..................................................................................................................... 58
4.7 Getting started.............................................................................................................................................. 60
4.8 Backwards compatibility..............................................................................................................................60
4.9 ITS.................................................................................................................................................................... 60
4.9.1 ITS cache control, locking, and test......................................................................................................61
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