Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Contents
4.9.2 ITS commands and errors.......................................................................................................................62
4.10 LPI caching...................................................................................................................................................63
4.11 Memory access and attributes............................................................................................................... 64
4.12 MSI-64.......................................................................................................................................................... 65
4.13 RAMs and ECC...........................................................................................................................................66
4.14 Performance Monitoring Unit................................................................................................................. 67
4.15 Reliability, Accessibility, and Serviceability........................................................................................... 68
4.15.1 Non-secure access................................................................................................................................. 69
4.15.2 Scrub..........................................................................................................................................................69
4.15.3 Error record classification..................................................................................................................... 69
4.15.4 ECC error reporting and recovery......................................................................................................69
4.15.5 Error recovery and fault handling interrupts....................................................................................70
4.15.6 Error handling records...........................................................................................................................71
4.15.7 Bus errors................................................................................................................................................. 87
4.16 Multichip operation................................................................................................................................... 88
4.16.1 Connecting the chips.............................................................................................................................89
4.16.2 Changing the Routing table owner.................................................................................................... 90
4.16.3 SPI ownership for multichip operation..............................................................................................91
4.16.4 Power control and P-Channel............................................................................................................. 91
4.16.5 Isolating a chip from the system........................................................................................................ 92
4.16.6 SPI operation for multichip operation............................................................................................... 93
4.16.7 LPI multichip operation......................................................................................................................... 94
5. Programmers model.....................................................................................................................................95
5.1 Register map pages......................................................................................................................................95
5.1.1 Discovery.....................................................................................................................................................97
5.1.2 GIC-600AE register access and banking.............................................................................................98
5.2 Distributor registers (GICD/GICDA) summary...................................................................................... 98
5.2.1 GICD_CTLR, Distributor Control Register........................................................................................ 101
5.2.2 GICD_TYPER, Interrupt Controller Type Register...........................................................................102
5.2.3 GICD_IIDR, Distributor Implementer Identification Register........................................................103
5.2.4 GICD_FCTLR, Function Control Register..........................................................................................104
5.2.5 GICD_SAC, Secure Access Control register.....................................................................................106
5.2.6 GICD_CHIPSR, Chip Status Register................................................................................................. 107
5.2.7 GICD_DCHIPR, Default Chip Register.............................................................................................. 109
5.2.8 GICD_CHIPR<n>, Chip Registers....................................................................................................... 109
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