Revision history RM0033
1360/1381 RM0033 Rev 9
13-Dec-2011 4
Specified register access for CRC, power controller, RCC, GPIOs,
SYSCFG, interrupts, DMA, ADC, DAC, timers, independent
watchdog, window watchdog, RNG, cryptographic processor, UART,
SPI, SDIO, CAN, USB OTG FS and HS, and FSMC.
Definition of reserved bits standardized to “Reserved, must be kept
at reset value”.
Updated disclaimer on last page.
PWR:
Removed notes below Figure 7: Low-power mode summary.
RCC:
Updated Section 5.2.7: Clock security system (CSS).
Updated HSERDY description in Section 5.3.1: RCC clock control
register (RCC_CR).
Updated PLLN and PLLQ in Section 5.3.2: RCC PLL configuration
register (RCC_PLLCFGR).
In Section 5.3.22: RCC spread spectrum clock generation register
(RCC_SSCGR), changed MODPER and INCSTEP in RCC_SSCGR
register bit mapping.
INTERRUPTS:
Updated Figure 19: External interrupt/event controller block diagram.
DMA:
Added note related to EN bit in Section 9.5.5: DMA stream x
configuration register (DMA_SxCR) (x = 0..7). Updated definition of
NDT[15:0] bits in Section 9.5.6: DMA stream x number of data
register (DMA_SxNDTR) (x = 0..7).
ADC:
Removed temperature sensor sampling time from Section 10.10:
Temperature sensor, and modified equation to calculate the
temperature in Section : Reading the temperature. Updated
Figure 29: Timing diagram. Updated AWDIE in
Section 10.13.2:
ADC control register 1 (ADC_CR1).
DAC:
TIMERS:
TIM1 and TIM8: Updated Section 13.3.3: Repetition counter and
modified Figure 85: Update rate examples depending on mode and
TIMx_RCR register settings.
TIM11/12/13/14: removed TRGO timer controller output in
Figure 113: General-purpose timer block diagram.
Table 224. Document revision history (continued)
Date Version Changes
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