RM0033 Rev 9 1361/1381
RM0033 Revision history
1375
13-Dec-2011
4
(continued)
RTC:
Updated Section 22.3.9: RTC coarse digital calibration.
Added note to DC[4:0] bit description in Section 22.6.7: RTC
calibration register (RTC_CALIBR).
I2C:
Updated Note in Section 23.6.8: I
2
C Clock control register
(I2C_CCR).
USART:
Updated Section 24.3: USART functional description to remove
IrDA_RDI and IrDA_TDO and removed IRDA_OUT and IRDA_IN
from Figure 223: USART block diagram.
Updated Section 24.3.11: Smartcard to specify that TX pin must be
configured as open drain.
Section 24.6.6: Control register 3 (USART_CR3): removed notes
related to UART5 in DMAT and DMAR description.
SPI:
Modified Section : Slave select (NSS) pin management and note
related to NSS in Section 25.3.3: Configuring the SPI in master
mode.
SDIO:
Updated SDIO/DMA interface configuration steps in Section 26.3.2:
SDIO APB2 interface.
Updated value and description for bits [45:40] and [7:1] in Table 129:
R4 response. Updated value at bits [45:40] in Table 131: R5
response.
USB OTG FS:
Updated INEPTXSA description in Section : OTG_FS device IN
endpoint transmit FIFO size register (OTG_FS_DIEPTXFx) (x = 1..3,
where x is the FIFO_number).
Changed PHYSEL from bit 7 to bit 6 of the Section : OTG_FS USB
configuration register (OTG_FS_GUSBCFG).
USB OTG HS:
Updated INEPTXSA description in Section : OTG_HS device IN
endpoint transmit FIFO size register (OTG_HS_DIEPTXFx) (x = 1..5,
where x is the FIFO_number).
Added PHYSEL and updated FSLSPCS for LS host mode in
Section : OTG_HS USB configuration register
(OTG_HS_GUSBCFG).
ETHERNET:
Updated standard for precision networked clock synchronization in
Section 28.1: Ethernet introduction and Section 28.1: Ethernet
introduction.
Table 224. Document revision history (continued)
Date Version Changes
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