Revision history RM0033
1362/1381 RM0033 Rev 9
13-Dec-2011
4
(continued)
FSMC:
Updated Section 31.3.1: Supported memories and transactions and
Section 31.3: AHB interface. Updated Section 27.4.2: Normal mode.
Changed Clock divide ration minimum value in Table 173:
Programmable NOR/PSRAM access parameters.
Added register access in Section 31.5.6: NOR/PSRAM control
registers and Section 31.6.8: NAND Flash/PC Card control registers
Updated Table 172: NOR Flash/PSRAM supported memories and
transactions for SRAM and ROM in asynchronous mode.
Updated Table 191: FSMC_BTRx bit fields, and Ta bl e 19 4 :
FSMC_BTRx bit fields.
Added Note 1 below Figure 399: Mode1 read accesses, and Note 1
below Figure 401: ModeA read accesses.
DEBUG:
Section 32.16.4: Debug MCU APB1 freeze register
(DBGMCU_APB1_FZ): added DBG_CAN2_STOP description for bit
26, and changed bit 24 to reserved. Updated bit 10 from reserved to
DBG_RTC_STOP in Table 223: DBG register map and reset values.
Electronic signature:
Added Section 33.2: Flash size in Section 33.1: Unique device ID
register (96 bits).
Table 224. Document revision history (continued)
Date Version Changes
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