ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Offset Name Type Reset Width Description Architecture
defined?
0x0040
GICR_SETLPIR
9
WO - 64 - Yes
0x0048
GICR_CLRLPIR
9
WO - 64 - Yes
0x0050-
0x006C
- - - - Reserved -
0x0070
GICR_PROPBASER
10
RW Configuration
dependent
64 Redistributor Properties Base Address Register Yes
0x0078
GICR_PENDBASER
10
RW
7
Configuration
dependent
64 Redistributor LPI Pending Table Base Address Register
We recommend that if possible, you set the
GICR_PENDBASER Pending Table Zero bit to one. This
setting reduces the power and time that is taken during
initialization.
Yes
0x0080-
0x009C
- - - - Reserved -
0x00A0
GICR_INVLPIR
9
WO - 64 - Yes
0x00A8-
0x00AC
- - - - Reserved -
0x00B0
GICR_INVALLR
9
WO - 64 - Yes
0x00B8-
0x00BC
- - - - Reserved -
0x00C0
GICR_SYNCR
9
RO 0x0 32 - Yes
0x00C4-
0xFFCC
- - - - Reserved -
0xFFD0 GICR_PIDR4 RO 0x44 32 Peripheral ID 4 Register No
0xFFD4 GICR_PIDR5 RO 0x00 32 Peripheral ID 5 Register No
0xFFD8 GICR_PIDR6 RO 0x00 32 Peripheral ID 6 Register No
0xFFDC GICR_PIDR7 RO 0x00 32 Peripheral ID 7 Register No
0xFFE0 GICR_PIDR0 RO 0x93 32 Peripheral ID 0 Register No
0xFFE4 GICR_PIDR1 RO 0xB4 32 Peripheral ID 1 Register No
0xFFE8 GICR_PIDR2 RO 0x3B 32 Peripheral ID 2 Register No
0xFFEC GICR_PIDR3 RO 0x00 32 Peripheral ID 3 Register No
0xFFF0 GICR_CIDR0 RO 0x0D 32 Component ID 0 Register No
0xFFF4 GICR_CIDR1 RO 0xF0 32 Component ID 1 Register No
0xFFF8 GICR_CIDR2 RO 0x05 32 Component ID 2 Register No
0xFFFC GICR_CIDR3 RO 0xB1 32 Component ID 3 Register No
9
This register is present only when Direct LPI registers are configured.
10
The existence of this register depends on the configuration of the GIC-600AE. If ITS and LPI support is not
included, this register does not exist.
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