ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Functional Safety
Figure 6-12: GIC topology with multiple clock domains
SPI Collator
ITS
GICD
ITS
I/O DEVICE
ASYNC
SPI
SPI
SPI
I/O DEVICE
ASYNC
REGSLICE
REGSLICE
Clock
Controller
ASYNC
ASYNC
REGSLICE
REGSLICE
ASYNC
ASYNC
ASYNC
ASYNC
ASYNC
ASYNC
ACE-Lite
subordinate
(Config)
ACE-Lite manager
Off-Chip IF
ASYNC
ASYNC
ITS IF
ASYNC
ASYNC
ASYNC
ASYNC
ICN
System interconnect
Clock
Controller
Clock
Controller
Clock
Controller
Clock
Controller
ASYNC ASYNC
ASYNC ASYNC
Cluster
Cluster
CORE
CPUIF
CPUIF
CORE
PPI PPI
CORE
CPUIF
CPUIF
CORE
PPI
PPI
Clock
Controller
Key
Clock Q-Channel
Power Q-Channel
P-Channel
The following figure shows a top-level example of a GIC topology with multiple power domains.
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