Arm
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CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Signal descriptions
Table A-6: ACE-Lite manager interface signals
Manager write address channel signals. Only present if LPI support is configured.
Signal Direction Description
Buses containing _its[_<num>] are used by the specific ITS for read/writes to the private tables and Command queue. Buses
without an _its suffix are used for accesses to the LPI Pending and Property tables. This port performs all accesses in monolithic
configurations.
awaddr_[its[_<num>]]_m[variable:0]
14
Output The write address gives the address of the first transfer in a write burst transaction.
awid_[its[_<num>]]_m[variable:0]
14
Output This signal is the identification tag for the write address group of signals.
awlen_[its[_<num>]]_m[7:0] Output The burst length gives the exact number of transfers in a burst. This information
determines the number of data transfers associated with the address.
awsize_[its[_<num>]]_m[2:0] Output This signal indicates the size of each transfer in the burst.
awburst_[its[_<num>]]_m[1:0] Output The burst type and size information determine how the address for each transfer within
the burst is calculated.
awprot_[its[_<num>]]_m[2:0] Output This signal indicates the privilege and security level of the transaction, and whether the
transaction is a data access or an instruction access.
awvalid_[its[_<num>]]_m Output This signal indicates that the channel is signaling valid write address and control
information.
awready_[its[_<num>]]_m Input This signal indicates that the channel is signaling valid write address and control
information.
awcache_[its[_<num>]]_m[3:0] Output This signal indicates how transactions are required to progress through a system.
awdomain_[its[_<num>]]_m[1:0] Output This signal indicates the Shareability domain of a write transaction.
awsnoop_[its[_<num>]]_m[3:0] Output This signal indicates the transaction type for Shareable write transactions.
awbar_[its[_<num>]]_m[1:0] Output This signal indicates a write barrier transaction.
awuser_[its[_<num>]]_m[variable:0]
14
Output Optional User signal. For an ITS switch, variable is a minimum of did_width−1.
Manager write data channel signals. Only present if LPI support is configured.
Signal Direction Description
wstrb_[its[_<num>]]_m[variable:0]
14
Output This signal indicates which byte lanes hold valid data. There is one write strobe bit for every
8 bits of the write data bus.
wdata_[its[_<num>]]_m[variable:0]
14
Output Write data
wvalid_[its[_<num>]]_m Output This signal indicates that valid write data and strobes are available.
wready_[its[_<num>]]_m Input This signal indicates that the subordinate can accept the write data.
wlast_[its[_<num>]]_m Output This signal indicates the last transfer in a write burst.
Manager write response channel signals. Only present if LPI support is configured.
Signal Direction Description
bid_[its[_<num>]]_m[variable:0]
14
Input This signal is the ID tag of the write response.
bvalid_[its[_<num>]]_m Input This signal indicates that valid write data and strobes are available.
bready_[its[_<num>]]_m Output This signal indicates that the channel is signaling a valid write response.
bresp_[its[_<num>]]_m[1:0] Input This signal indicates the status of the write transaction.
buser_[its[_<num>]]_m[n:0] Input Write response User signal, where n = axis_buser_width−1
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