ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Signal descriptions
Signal Direction Description
its_id[7:0] Input An ID number that identifies the ITS block in the system. Software can read the
GITS_CFGID register to access the value of this signal. It must be tied to the ic<x>dtdest
signal value that is used to read the ITS using the AXI4-Stream interface.
fault_int Output Fault handling interrupt. The GIC-600AE can deliver this interrupt internally but the output
is provided for any other device such as a system control processor that does not receive
normal interrupts from the GIC. See 4.15.5 Error recovery and fault handling interrupts on
page 70.
err_int Output Error handling interrupt. The GIC-600AE can deliver this interrupt internally but the output
is provided for any other device such as a system control processor that does not receive
normal interrupts from the GIC. See 4.15.5 Error recovery and fault handling interrupts on
page 70.
pmu_int Output PMU counter overflow interrupt. This signal is a level-sensitive interrupt. The GIC-600AE
can deliver this interrupt internally but the output is provided as an external output to
trigger an external agent to service the GIC, for example, to read out the PMU counter
snapshot registers. See Overflow interrupt on page 68.
sample_req Input Request from a Cross Trigger Interface (CTI) to sample the PMU counters. Equivalent to
writing to the GICP_CAPR register. See Snapshot on page 68 for more information.
sample_ack Output This signal goes HIGH when the GIC acknowledges the PMU sample request from the CTI
gict_allow_ns Input From reset, this tie-off signal controls whether Non-secure software can access the GICT
Error Record registers
gicp_allow_ns Input From reset, this tie-off signal controls whether Non-secure software can access the GICP
PMU registers
gicd_page_offset Input From reset, this tie-off signal controls the page address bits[x:16] of the GICD page. Only
present in monolithic configurations. See Page offset on page 96.
its_transr_page_offset Input From reset, this tie-off signal controls the page address of the GITS_TRANSLATER register.
Only present in monolithic configurations. See 4.12 MSI-64 on page 65 and Page offset on
page 96.
target_address<n>[ADDR_WIDTH
−17:0]
Input Modifies the address map to ensure only writes to the correct location can trigger MSI
requests. Only present when the bypass switch is configured. <n> represents an ITS
identifier.
Specifies the 64K page address that includes the GITS_TRANSLATER register address,
and is matched against the axaddr[ADDR_WIDTH−1:16] signal. See 3.3.1 ITS ACE-Lite
subordinate interface on page 36.
msi_translator_page Input The target page address of the GITS_TRANSLATER register. The MSI-64 Encapsulator
does not support an msi_transalator_page signal value of 0. See 3.4 MSI-64 Encapsulator
on page 40.
msi64_translator_page Input The target address of the 64-bit GITS_TRANSLATER register. This page must be at a
different location to the msi_translator_page signal and at a location that is known only
to the hypervisor. The hypervisor must be able to protect the page from accesses from
devices and processors that can spoof incorrect DeviceIDs. See 3.4 MSI-64 Encapsulator
on page 40 and 4.12 MSI-64 on page 65.
awdeviceid Input The ACE-Lite AW sideband signal that reports the DeviceID for writes to
GITS_TRANSLATER. The value is ignored for non-MSI writes. See 3.4 MSI-64 Encapsulator
on page 40 and 3.4.1 MSI-64 ACE-Lite interfaces on page 40.
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