Infineon TriCore TC1.6P User Manual

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-57
CACHEI.WI
Cache Index, Writeback, Invalidate
Description
If the cache line at the memory index/way specified by the address register A[b] is present in the L1 data cache,
write back the modified data and then invalidate the line in the L1 data cache.
The address specified by the address register A[b] undergoes standard protection checks. Address register
updates associated with the addressing mode are performed regardless of the cache operation.
The location of way/index within A[b] is implementation dependent.
CACHEI.WIA[b], off10 (BO)(Base + Short Offset Addressing Mode)
index_way = A[b] + sign_ext(off10);
cache_index_wi(index_way);
CACHEI.WIA[b], off10 (BO)(Post-increment Addressing Mode)
index_way = A[b];
cache_index_wi(index_way);
A[b] = index_way + sign_ext(off10);
CACHEI.WIA[b], off10 (BO)(Pre-increment Addressing Mode)
index_way = A[b] + sign_ext(off10);
cache_index_wi(index_way);
A[b] = index_way;
Status Flags
Examples
cachei.wi [a3]4
cachei.wi [+a3]4
cachei.wi [a3+]4
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
off10[9:6]
28 27
2F
H
22 21
off10[5:0]
16 15
b
12 11
-
8 7
89
H
0
31
off10[9:6]
28 27
0F
H
22 21
off10[5:0]
16 15
b
12 11
-
8 7
89
H
0
31
off10[9:6]
28 27
1F
H
22 21
off10[5:0]
16 15
b
12 11
-
8 7
89
H
0

Infineon TriCore TC1.6P Specifications

General

Brand	Infineon
Model	TriCore TC1.6P
Category	Microcontrollers
Language	English