TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-89
DVINIT
Divide-Initialization Word
DVINIT.U
Divide-Initialization Word Unsigned
DVINIT.B
Divide-Initialization Byte
DVINIT.BU
Divide-Initialization Byte Unsigned
DVINIT.H
Divide-Initialization Half-word
DVINIT.HU
Divide-Initialization Half-word Unsigned
Description
The DVINIT group of instructions prepare the operands for a subsequent DVSTEP instruction (see DVSTEP) from
the dividend D[a] and divisor D[b], and also check for conditions that will cause overflow of the final quotient result.
After a DVINIT instruction E[c] contains the partially calculated remainder (equal to the sign-extended dividend)
and partially calculated quotient (equal to + or - zero in ones complement format, depending on the signs of the
dividend and divisor).
For signed operands DVINIT, DVINIT.H or DVINIT.B must be used. For unsigned operands DVINIT.U, DVINIT.HU
and DVINIT.BU are used.
The size of the remainder and quotient bit fields in E[c] depend upon the variant of DVINIT used, which in turn
depends upon the number of subsequent DVSTEP instructions required to calculate the final remainder and
quotient results.
If the final quotient result is guaranteed to fit into 8 bits then a DVINIT.B(U) can be used, but must be followed by
only one DVSTEP instruction.
If the quotient result is guaranteed to fit into 16 bits then a DVINIT.H(U) can be used but must be followed by two
DVSTEP instructions.
For a quotient result of 32 bits a DVINIT(.U) must be used, followed by four DVSTEP instructions.
The resultant bit fields in E[c] are as follows:
• DVINIT(.U) E[c][63:0] = partially calculated remainder.
• DVINIT.H(U) E[c][63:16] = partially calculated remainder, E[c][15:0] = partially calculated quotient.
• DVINIT.B(.U) E[c][63:24] = partially calculated remainder, E[c][23:0] = partially calculated quotient.
The .B(U) and .H(U) suffixes of the DVINIT group of instructions indicate an 8-bit and 16-bit quotient result, not 8-
bit and16-bit operands as in other instructions. The operands supplied to a DVINIT, DVINIT.H or DVINIT.B
instruction are required to be 32-bit sign-extended values. The operands supplied to the DVINIT.U, DVINIT.HU
and DVINIT.BU instructions are 32-bit zero-extended values.
Overflow occurs if the divisor is zero, or if the dividend is the maximum negative value for the instruction variant
and the divisor is minus one. No check is performed to ensure that the expected quotient can be represented in
32, 16, 8 bits, depending on the DVINIT variant used.
DVINIT.BE[c], D[a], D[b] (RR)
31
c
28 27
5A
H
20 19
-
18 17
0
H
16 15
b
12 11
a
8 7
4B
H
0
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