TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-367
SUB
Subtract
Description
Subtract the contents of data register D[b] from the contents of data register D[a] and put the result in data register
D[c]. The operands are treated as 32-bit integers.
SUBD[c], D[a], D[b] (RR)
result = D[a] - D[b];
D[c] = result[31:0];
SUBD[a], D[b] (SRR)
SUBD[a], D[15], D[b] (SRR)
SUBD[15], D[a], D[b] (SRR)
Status Flags
Subtract the contents of data register D[b] from the contents of either data register D[a] or D[15] and put the result
in either data register D[a] or D[15]. The operands are treated as 32-bit integers.
result = D[a] - D[b];
D[a] = result[31:0];
result = D[15] - D[b];
D[a] = result[31:0];
result = D[a] - D[b];
D[15] = result[31:0];
C Not set by this instruction.
V overflow = (result > 7FFFFFFF
H
) OR (result < -80000000
H
);
if (overflow) then PSW.V = 1 else PSW.V = 0;
SV if (overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
31
c
28 27
08
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0