TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-79
CSUB
Conditional Subtract
Description
If the contents of data register D[d] are not zero, subtract the contents of data register D[b] from the contents of
data register D[a] and put the result in data register D[c]; otherwise put the contents of D[a] in D[c].
CSUBD[c], D[d], D[a], D[b] (RRR)
condition = (D[d] != 0);
result = ((condition) ? D[a] - D[b] : D[a]);
D[c] = result[31:0];
Status Flags
Examples
csub d3, d4, d1, d2
See Also
CADD, CADDN, CMOV (16-bit), CMOVN (16-bit), CSUBN, SEL, SELN
C Not set by this instruction.
V overflow = (result > 7FFFFFFF
H
) OR (result < -80000000
H
);
if(condition) then PSW.V = overflow else PSW.V = PSW.V;
SV if (condition AND overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
AV advanced_overflow = result[31] ^ result[30];
if (condition) then PSW.AV = advanced_overflow else PSW.AV = PSW.AV;
SAV if (condition AND advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV;
31
c
28 27
d
24 23
02
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
2B
H
0
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