Infineon TriCore TC1.6P - OR - Bitwise or

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-297
OR
Bitwise OR
Description
Compute the bitwise OR of the contents of data register D[a] and the contents of either data register D[b]
(instruction format RR) or const9 (instruction format RC). Put the result in data register D[c]. The const9 value is
zero-extended.
ORD[c], D[a], const9 (RC)
D[c] = D[a] | zero_ext(const9);
ORD[c], D[a], D[b] (RR)
D[c] = D[a] | D[b];
ORD[15], const8 (SC)
ORD[a], D[b] (SRR)
Status Flags
Compute the bitwise OR of the contents of either data register D[a] (instruction format SRR) or D[15] (instruction
format SC) and the contents of either data register D[b] (format SRR) or const8 (format SC). Put the result in
either data register D[a] (format SRR) or D[15] (format SC). The const8 value is zero-extended.
D[15] = D[15] | zero_ext(const8);
D[a] = D[a] | D[b];
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
c
28 27
0A
H
21 20
const9
12 11
a
8 7
8F
H
0
31
c
28 27
0A
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0F
H
0
15
const8
8 7
96
H
0
15
b
12 11
a
8 7
A6
H
0