Infineon TriCore TC1.6P - MADDSUR.H - Packed Multiply-Add;Subtract Q Format with Rounding; Packed Multiply-Add;Subtract Q Format with Rounding Saturated

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-214
MADDSUR.H
Packed Multiply-Add/Subtract Q Format with Rounding
MADDSURS.H
Packed Multiply-Add/Subtract Q Format with Rounding Saturated
Description
Multiply two signed 16-bit (half-word) values. Add (subtract) the product (left justified if n == 1) to (from) a signed
16-bit value and put the rounded result into half of a 32-bit register (Note that since there are two results, the two
register halves are used). There are four cases of half-word multiplication:
• 16U * 16U, 16L * 16L
• 16U * 16L, 16L * 16U
• 16U * 16L, 16L * 16L
• 16L * 16U, 16U * 16U
Note that n should only take the values 0 or 1, any other value returns an undefined result. If (n == 1) then 8000
H
* 8000
H
= 7FFFFFFF
H
(for signed 16-bit * 16-bit multiplications only).
MADDSUR.HD[c], D[d], D[a], D[b] LL, n (RRR1)
16U * 16L +||- (16U * 16L || 16L * 16L) rounded --> 16||16
sc1 = (D[a][31:16] == 8000
H
) AND (D[b][15:0] == 8000
H
) AND (n == 1);
sc0 = (D[a][15:0] == 8000
H
) AND (D[b][15:0]] == 8000
H
) AND (n == 1);
mul_res1 = sc1 ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][15:0]) << n);
mul_res0 = sc0 ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][15:0]) << n);
result_halfword1 = {D[d][31:16], 16’b0} + mul_res1 + 8000
H
;
result_halfword0 = {D[d][15:0], 16’b0} - mul_res0 + 8000
H
;
D[c] = {result_halfword1[31:16], result_halfword0[31:16]}; // Packed short fraction
MADDSUR.HD[c], D[d], D[a], D[b] LU, n (RRR1)
16U || 16L +||- (16U * 16L || 16L * 16U) rounded --> 16||16
sc1 = (D[a][31:16] == 8000
H
) AND (D[b][15:0] == 8000
H
) AND (n == 1);
sc0 = (D[a][15:0] == 8000
H
) AND (D[b][31:16]] == 8000
H
) AND (n == 1);
mul_res1 = sc1 ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][15:0]) << n);
mul_res0 = sc0 ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][31:16]) << n);
result_halfword1 = {D[d][31:16], 16’b0} + mul_res1 + 8000
H
;
result_halfword0 = {D[d][15:0], 16’b0} - mul_res0 + 8000
H
;
D[c] = {result_halfword1[31:16], result_halfword0[31:16]}; // Packed short fraction
MADDSUR.HD[c], D[d], D[a], D[b] UL, n (RRR1)
16U || 16L +||- (16U * 16U || 16L * 16L) rounded --> 16||16
31
c
28 27
d
24 23
0E
H
18 17
n
16 15
b
12 11
a
8 7
C3
H
0
31
c
28 27
d
24 23
0D
H
18 17
n
16 15
b
12 11
a
8 7
C3
H
0