TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-290
NE
Not Equal
Description
If the contents of data register D[a] are not equal to the contents of either data register D[b] (instruction format RR)
or const9 (instruction format RC), set the least-significant bit of D[c] to one and clear the remaining bits to zero;
otherwise clear all bits in D[c]. The const9 value is sign-extended.
NED[c], D[a], const9 (RC)
result = (D[a] != sign_ext(const9));
D[c] = zero_ext(result);
NED[c], D[a], D[b] (RR)
result = (D[a] != D[b]);
D[c] = zero_ext(result);
Status Flags
Examples
ne d3, d1, d2
ne d3, d1, #126
See Also
EQ, GE, GE.U, LT, LT.U, EQANY.B, EQANY.H, NEZ.A
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
c
28 27
11
H
21 20
const9
12 11
a
8 7
8B
H
0
31
c
28 27
11
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0
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