TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-97
EQ.A
Equal to Address
Description
If the contents of address registers A[a] and A[b] are equal, set the least-significant bit of D[c] to one and clear the
remaining bits to zero; otherwise clear all bits in D[c].
EQ.AD[c], A[a], A[b] (RR)
D[c] = (A[a] == A[b]);
Status Flags
Examples
eq.a d3, a4, a2
See Also
EQZ.A, GE.A, LT.A, NE, NEZ.A
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
c
28 27
40
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
01
H
0