Infineon TriCore TC1.6P User Manual

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-53
CACHEI.W
Cache Index, Writeback
Description
If any modified cache line at the memory index/way specified by address register A[b] is present in the L1 data
cache, writeback the modified data. The line will still be present within the L1 data cache but will be marked as
unmodified.
The address specified by the address register A[b] undergoes standard protection checks. Address register
updates associated with the addressing mode are performed regardless of the cache operation.
The location of way/index within A[b] is implementation dependent.
CACHEI.WA[b], off10 (BO)(Base + Short Offset Addressing Mode)
index_way = A[b] + sign_ext(off10);
cache_index_wb(index_way);
CACHEI.WA[b], off10 (BO)(Post-increment Addressing Mode)
index_way = A[b];
cache_index_wb(index_way);
A[b] = index_way + sign_ext(off10);
CACHEI.WA[b], off10 (BO)(Pre-increment Addressing Mode)
index_way = A[b] + sign_ext(off10);
cache_index_wb(index_way);
A[b] = index_way;
Status Flags
Examples
cachei.w [a3]4
cachei.w [+a3]4
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
off10[9:6]
28 27
2B
H
22 21
off10[5:0]
16 15
b
12 11
-
8 7
89
H
0
31
off10[9:6]
28 27
0B
H
22 21
off10[5:0]
16 15
b
12 11
-
8 7
89
H
0
31
off10[9:6]
28 27
1B
H
22 21
off10[5:0]
16 15
b
12 11
-
8 7
89
H
0

Infineon TriCore TC1.6P Specifications

General

Brand	Infineon
Model	TriCore TC1.6P
Category	Microcontrollers
Language	English