Infineon TriCore TC1.6P - Page 99

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-52
EA = A[b];
cache_address_wi(EA);
A[b] = EA + sign_ext(off10);
CACHEA.WIA[b], off10 (BO)(Pre-increment Addressing Mode)
EA = A[b] + sign_ext(off10);
cache_address_wi(EA);
A[b] = EA;
Status Flags
Examples
cachea.wi [a3]4
cachea.wi [+a3]4
cachea.wi [a3+]4
cachea.wi [a4/a5+c]4
cachea.wi [a4/a5+r]
See Also
CACHEA.I, CACHEA.W, CACHEI.I, CACHEI.W, CACHEI.WI
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
off10[9:6]
28 27
0D
H
22 21
off10[5:0]
16 15
b
12 11
-
8 7
89
H
0
31
off10[9:6]
28 27
1D
H
22 21
off10[5:0]
16 15
b
12 11
-
8 7
89
H
0