TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Overview
V1.0 2013-07
User Manual (Volume 2) 2-21
The Insert Mask (IMASK) instruction can be used in conjunction with the Load Modify Store (LDMST) instruction,
to store a single bit or a bit field to a location in memory, using any of the addressing modes. This operation is
especially useful for reading and writing memory-mapped peripherals.
The IMASK instruction is very similar to the INSERT instruction, but IMASK generates a data register pair that
contains a mask and a value. The LDMST instruction uses the mask to indicate which portion of the word to modify.
An example of a typical instruction sequence is:
imask E8, 3, 4, 2; // insert value = 3, position = 4, width = 2
ldmst _IOREG, E8; // at absolute address "_IOREG"
To clarify the operation of the IMASK instruction, consider the following example. The binary value 1011B is to be
inserted starting at bit position 7 (the width is four). The IMASK instruction would result in the following two values:
0000 0000 0000 0000 0000 0111 1000 0000B MASK
0000 0000 0000 0000 0000 0101 1000 0000B VALUE
To store a single bit with a variable bit offset from a word-aligned byte pointer, the word address is first determined
in the same way as for the load above.
The special scaled offset instruction shifts the bit offset to the right by three positions, which produces a byte offset,
then adds this offset to the byte pointer above.
Finally it zeros out the two lower bits, so aligning the access on a word boundary.
An IMASK and LDMST instruction can store the bit into the proper position in the word. An example is:
ADDSC.AT A8, A9, D8; // A9 = byte pointer. D8 = bit offset.
IMASK E10, D9, D8, 1; // D9[0] = data bit.
LDMST [A8], E10
2.11 Context Related Instructions
Besides the instructions that implicitly save and restore contexts (such as Calls and Returns), the TriCore
instruction set includes instructions that allow a task’s contexts to be explicitly saved, restored, loaded, and stored.
These instructions are detailed here.
2.11.1 Lower Context Saving and Restoring
The upper context of a task is always automatically saved on a call, interrupt or trap, and is automatically restored
on a return. However the lower context of a task must be explicitly saved or restored.
The SVLCX instruction (Save Lower Context) saves registers A[2] through A[7] and D[0] through D[7], together
with the return address (RA) in register A[11] and the PCXI. This operation is performed when using the FCX and
PCX pointers to manage the CSA lists.
The RSLCX instruction (Restore Lower Context) restores the lower context. It loads registers A[2] through A[7]
and D[0] through D[7] from the CSA. It also loads A[11] (Return Address) from the saved PC field. This operation
is performed when using the FCX and PCX pointers to manage the CSA lists.
The BISR instruction (Begin Interrupt Service Routine) enables the interrupt system (ICR.IE = 1), allows the
modification of the CPU priority number (CCPN), and saves the lower context in the same manner as the SVLCX
instruction.
2.11.2 Context Loading and Storing
The effective address of the memory area where the context is stored to or loaded from, is part of the Load or
Store instruction. The effective address must resolve to a memory location aligned on a 16-word boundary,
otherwise a data address alignment trap (ALN) is generated.
The STUCX instruction (Store Upper Context) stores the same context information that is saved with an implicit
upper context save operation: Registers A[10] to A[15] and D[8] to D[15], and the current PSW and PCXI.
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