TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-182
LT.W
Less Than Packed Word
LT.WU
Less Than Packed Word Unsigned
Description
If the contents of data register D[a] are less than the contents of data register D[b], set all bits in D[c] to one;
otherwise clear all bits in D[c]. D[a] and D[b] are treated as either signed (LT.W) or unsigned (LT.WU) 32-bit
integers.
LT.WD[c], D[a], D[b] (RR)
D[c] = (D[a] < D[b]) ? 32’hFFFFFFFF : 32’h00000000;
LT.WUD[c], D[a], D[b] (RR)
D[c] = (D[a] < D[b]) ? 32’hFFFFFFFF : 32’h00000000; // unsigned
Status Flags
Examples
lt.w d3, d1, d2
lt.wu d3, d1, d2
See Also
EQ.B, EQ.H, EQ.W, LT.B, LT.BU, LT.H, LT.HU
C Not set by these instructions.
V Not set by these instructions.
SV Not set by these instructions.
AV Not set by these instructions.
SAV Not set by these instructions.
31
c
28 27
92
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0
31
c
28 27
93
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0