TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Information
V1.0 2013-07
User Manual (Volume 2) 1-9
1.3.2 Cache RTL Functions
CACHE[ ] is a syntactic structure which hides the implementation characteristics of the cache implemented.
CACHE can be associatively accessed either by:
• A single argument which is an address.
• Two arguments consisting of implementation defined ranges for set_index and set_element.
In either case the CACHE[ ] access returns a structure with:
• Boolean validity information (CACHE[ ].valid).
• Boolean data modification information (CACHE[ ].modified).
• Physical address of the copied location (CACHE[ ].physical_address).
• Stored data associated with the address (CACHE[ ].data).
The cache function descriptions are given in the following table.
Notes
1. ‘cacheline’, which appears in the cache function descriptions, is the size of the cache line in bytes and is
implementation dependent.
2. ‘index’ and ‘elem’, which appear in the cache function descriptions, are the set_index and set_element values.
These values are implementation dependent.
Table 1-10 Cache Functions
Function Definition
cache_address_ivld(EA) if (CACHE[EA].valid==1) then CACHE [EA].valid=0;
cache_address_wb(EA) if ((CACHE[EA].valid==1) AND (CACHE[EA].modified==1)) then {
pa = CACHE[EA].physical_address;
M[pa,cacheline] = CACHE[EA].data;
CACHE[EA].modified = 0;
}
cache_address_wi(EA) if (CACHE[EA].valid==1) then {
if (CACHE[EA].modified==1) then {
pa = CACHE[EA].physical_address;
M[pa,cacheline] = CACHE[EA].data;
}
CACHE[EA].modified = 0;
CACHE[EA].valid = 0;
}
cache_index_ivld if (CACHE[index,elem].valid = = 1) then CACHE[index,elem].valid = 0;
cache_index_wb if ((CACHE[index,elem].valid==1) AND (CACHE[index,elem].modified==1))
then {
pa = CACHE[index,elem].physical_address;
M[pa,cacheline] = CACHE[index,elem].data;
CACHE[index,elem].modified = 0;
}