Infineon TriCore TC1.6P User Manual

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-43
BISR
Begin Interrupt Service Routine
Description
Note:BISR can only be executed in Supervisor mode.
Save the lower context by storing the contents of A[2]-A[7], D[0]-D[7], and the current A[11] (return address) to the
current memory location pointed to by the FCX.
Set the current CPU priority number (ICR.CCPN) to the value of either const9[7:0] (instruction format RC) or
const8 (instruction format SC), and enable interrupts (set ICR.IE to one).
This instruction is intended to be one of the first executed instructions in an interrupt routine. If the interrupt routine
has not altered the lower context, the saved lower context is from the interrupted task. If a BISR instruction is
issued at the beginning of an interrupt, then an RSLCX instruction should be performed before returning with the
RFE instruction.
BISRconst9 (RC)
if (FCX == 0) trap(FCU);
tmp_FCX = FCX;
EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0};
new_FCX = M(EA, word);
M(EA,16 * word) = {PCXI, A[11], A[2], A[3], D[0], D[1], D[2], D[3], A[4], A[5], A[6], A[7], D[4], D[5], D[6], D[7]};
PCXI.PCPN = ICR.CCPN;
PCXI.PIE = ICR.IE;
PCXI.UL = 0;
PCXI[19:0] = FCX[19:0];
FCX[19:0] = new_FCX[19:0];
ICR.IE = 1;
ICR.CCPN = const9[7:0];
if (tmp_FCX == LCX) trap(FCD);
BISRconst8 (SC)
tmp_FCX = FCX;
31
-
28 27
00
H
21 20
const9
12 11
-
8 7
AD
H
0
15
const8
8 7
E0
H
0

Infineon TriCore TC1.6P Specifications

General

Brand	Infineon
Model	TriCore TC1.6P
Category	Microcontrollers
Language	English