TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-94
ENABLE
Enable Interrupts
Description
Note:ENABLE can only be executed in User-1 or Supervisor mode.
Enable interrupts by setting the Interrupt Enable bit (ICR.IE) in the Interrupt Control Register (ICR) to one.
ENABLE(SYS)
ICR.IE = 1;
Status Flags
Examples
enable
See Also
BISR, DISABLE, RESTORE
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
-
28 27
0C
H
22 21
-
12 11
-
8 7
0D
H
0
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