Infineon TriCore TC1.6P - EQ - Equal

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-95
EQ
Equal
Description
If the contents of data register D[a] are equal to the contents of either data register D[b] (instruction format RR) or
const9 (instruction format RC), set the least-significant bit of D[c] to one and clear the remaining bits to zero;
otherwise clear all bits in D[c]. The const9 value is sign-extended.
EQD[c], D[a], const9 (RC)
result = (D[a] == sign_ext(const9));
D[c] = zero_ext(result);
EQD[c], D[a], D[b] (RR)
result = (D[a] == D[b]);
D[c] = zero_ext(result);
EQD[15], D[a], const4 (SRC)
EQD[15], D[a], D[b] (SRR)
Status Flags
If the contents of data register D[a] are equal to the contents of either data register D[b] (instruction format SRR)
or const4 (instruction format SRC), set the least-significant bit of D[15] to 1 and clear the remaining bits to zero;
otherwise clear all bits in D[15]. The const4 value is sign-extended.
result = (D[a] == sign_ext(const4));
D[15] = zero_ext(result);
result = (D[a] == D[b]);
D[15] = zero_ext(result);
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
31
c
28 27
10
H
21 20
const9
12 11
a
8 7
8B
H
0
31
c
28 27
10
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0
15
const4
12 11
a
8 7
BA
H
0
15
b
12 11
a
8 7
3A
H
0