Infineon TriCore TC1.6P User Manual

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-49
CACHEA.W
Cache Address, Writeback
Description
If the cache line containing the byte memory location specified by the addressing mode is present in the L1 data
cache, write back any modified data. The line will still be present in the L1 data cache and will be marked as
unmodified.
If the cache line containing the byte memory location specified by the addressing mode is not present in the L1
data cache, then no operation should be performed in the L1 data cache. Specifically a refill of the line containing
the byte pointed to by the effective address should not be performed. Any address register updates associated
with the addressing mode are always performed regardless of the cache operation. The effective address is a
virtual address when operating in virtual mode.
CACHEA.WA[b], off10 (BO) (Base + Short Offset Addressing Mode)
EA = A[b] + sign_ext(off10);
cache_address_wb(EA);
CACHEA.WP[b] (BO) (Bit-reverse Addressing Mode)
index = zero_ext(A[b+1][15:0]);
incr = zero_ext(A[b+1][31:16]);
EA = A[b] + index;
cache_address_wb(EA);
new_index = reverse16(reverse16(index) + reverse16(incr));
A[b+1] = {incr[15:0], new_index[15:0]};
CACHEA.WP[b], off10 (BO)(Circular Addressing Mode)
index = zero_ext(A[b+1][15:0]);
length = zero_ext(A[b+1][31:16]);
EA = A[b] + index;
cache_address_wb(EA);
new_index = index + sign_ext(off10);
new_index = new_index < 0 ? new_index+length : new_index % length;
A[b+1] = {length[15:0], new_index[15:0]};
CACHEA.WA[b], off10 (BO) (Post-increment Addressing Mode)
31
off10[9:6]
28 27
2C
H
22 21
off10[5:0]
16 15
b
12 11
-
8 7
89
H
0
31
-
28 27
0C
H
22 21
-
16 15
b
12 11
-
8 7
A9
H
0
31
off10[9:6]
28 27
1C
H
22 21
off10[5:0]
16 15
b
12 11
-
8 7
A9
H
0

Infineon TriCore TC1.6P Specifications

General

Brand	Infineon
Model	TriCore TC1.6P
Category	Microcontrollers
Language	English