Infineon TriCore TC1.6P - SH.LT - Shift Less than; SH.LT.U - Shift Less than Unsigned

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-335
SH.LT
Shift Less Than
SH.LT.U
Shift Less Than Unsigned
Description
Left shift D[c] by one. If the contents of data register D[a] are less than the contents of either data register D[b]
(instruction format RR) or const9 (instruction format RC), set the least-significant bit of D[c] to one; otherwise set
the least-significant bit of D[c] to zero.
D[a] and either D[b] (format RR) or const9 (format RC) are treated as signed (SH.LT) or unsigned (SH.LT.U)
integers. The value const9 is sign-extended (SH.LT) or zero-extended (SH.LT.U).
SH.LTD[c], D[a], const9 (RC)
D[c] = {D[c][30:0], (D[a] < sign_ext(const9))};
SH.LTD[c], D[a], D[b] (RR)
D[c] = {D[c][30:0], (D[a] < D[b])};
SH.LT.UD[c], D[a], const9 (RC)
D[c] = {D[c][30:0], (D[a] < zero_ext(const9))}; // unsigned
SH.LT.UD[c], D[a], D[b] (RR)
D[c] = {D[c][30:0], (D[a] < D[b])}; // unsigned
Status Flags
C Not set by these instructions.
V Not set by these instructions.
SV Not set by these instructions.
AV Not set by these instructions.
SAV Not set by these instructions.
31
c
28 27
39
H
21 20
const9
12 11
a
8 7
8B
H
0
31
c
28 27
39
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0
31
c
28 27
3A
H
21 20
const9
12 11
a
8 7
8B
H
0
31
c
28 27
3A
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0