Infineon TriCore TC1.6P - LS and IP Instruction Summary Lists

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-420
3.3 LS and IP Instruction Summary Lists
This section contains two lists; one of the LS instructions and one of the IP instructions.
3.3.1 List of LS Instructions
• ADD.A - Add Address
• ADDIH.A - Add Immediate High to Address
• ADDSC.A - Add Scaled Index to Address
• ADDSC.AT - Add Bit-Scaled Index to Address
• BISR - Begin Interrupt Service Routine
• CACHEA.I - Cache Address, Invalidate
• CACHEA.W - Cache Address, Writeback
• CACHEA.WI - Cache Address, Writeback and Invalidate
• CACHEI.W - Cache Index, Writeback
• CACHEI.I - Cache Index, Invalidate
• CACHEI.WI - Cache Index, Writeback, Invalidate
• CALL - Call
• CALLA - Call Absolute
• CALLI - Call Indirect
• CMPSWAP.W - Compare and Swap
• DEBUG - Debug
• DISABLE - Disable Interrupts
• DSYNC - Synchronize Data
• ENABLE - Enable Interrupts
• EQ.A - Equal to Address
• EQZ.A - Equal Zero Address
• FCALL - Fast Call
• FCALLA - Fast Call Absolute
• FCALLI - Fast Call Indirect
• FRET - Return from Fast Call
• GE.A - Greater Than or Equal Address
• ISYNC - Synchronize Instructions
• J - Jump Unconditional
• JA - Jump Unconditional Absolute
• JEQ.A - Jump if Equal Address
• JI - Jump Indirect
• JL - Jump and Link
• JLA - Jump and Link Absolute
•
JLI - Jump and Link Indirect
• JNE.A - Jump if Not Equal Address
• JNZ.A - Jump if Not Equal to Zero Address
• JZ.A - Jump if Zero Address
• LD.A - Load Word to Address Register
• LD.B - Load Byte
• LD.BU - Load Byte Unsigned
• LD.D - Load Double-word
• LD.DA - Load Double-word to Address Register
• LD.H - Load Half-word
• LD.HU - Load Half-word Unsigned
• LD.Q - Load Half-word Signed Fraction