TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Overview
V1.0 2013-07
User Manual (Volume 2) 2-11
2.5 Compare Instructions
The compare instructions perform a comparison of the contents of two registers.
The Boolean result (1 = true and 0 = false) is stored in the least-significant bit of a data register. The remaining
bits in the register are cleared to zero.
2.5.1 Simple Compare
Figure 2-8 illustrates the operation of the LT (Less Than) compare instruction:
Figure 2-8 LT (Less Than) Comparison
The comparison instructions are:
• EQ (Equal)
• NE (Not Equal)
• LT (Less Than)
• GE (Greater than or Equal to)
Versions for both signed and unsigned integers are available.
Comparison conditions not explicitly provided in the instruction set can be obtained by either swapping the
operands when comparing two registers, or by incrementing the constant by one when comparing a register and
a constant (See Table 2-1).
2.5.2 Accumulating Compare
To accelerate the computation of complex conditional expressions, accumulating versions of the comparison
instructions are supported.
These instructions, indicated in the instruction mnemonic by ‘op’ preceding the ‘.’ (for example, op.LT), combine
the result of the comparison with a previous comparison result.
The combination is a logic AND, OR, or XOR; for example, AND.LT, OR.LT, and XOR.LT.
Figure 2-9 illustrates the combination of the LT instruction with a Boolean operation.
Table 2-1 Equivalent Comparison Operations
Implicit Comparison Operation TriCore Equivalent Comparison Operation
LE D[c], D[a], D[b] GE D[c], D[b], D[a]
LE D[c], D[a], const LT D[c], D[a], (const+1)
GT D[c], D[a], D[b] LT D[c], D[b], D[a]
GT D[c], D[a], const GE D[c], D[a], (const+1)
TC1051B
A
D[a] D[b]
A < B?
B
31 0 31 0
D[c]
031
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