Infineon TriCore TC1.6P User Manual

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-243
MSUB.Q
Multiply-Subtract Q Format
MSUBS.Q
Multiply-Subtract Q Format, Saturated
Description
Multiply two signed 16-bit or 32-bit values, subtract the product (left justified if n == 1) from a signed 32-bit or 64-
bit value and put the result into a 32-bit or 64-bit register.
There are eight cases of 16*16 operations, eight cases of 16*32 operations and four cases of 32*32 operations.
The MSUBS.Q result is saturated on overflow.
Note that n should only take the values 0 or 1, any other value returns an undefined result. If (n == 1) then 8000
H
* 8000
H
= 7FFFFFFF
H
(for signed 16-bit * 16-bit multiplications only).
MSUB.QD[c], D[d], D[a], D[b], n (RRR1)
32 - (32 * 32)Up --> 32
result = D[d] - (((D[a] * D[b]) << n) >> 32);
D[c] = result[31:0]; // Fraction
MSUB.QE[c], E[d], D[a], D[b], n (RRR1)
64 - (32 * 32) --> 64
result = E[d] - ((D[a] * D[b]) << n);
E[c] = result[63:0]; // Multi-precision fraction
MSUB.QD[c], D[d], D[a], D[b] L, n (RRR1)
32 - (32 * 16L)Up --> 32
result = D[d] - (((D[a] * D[b][15:0]) << n) >> 16);
D[c] = result[31:0]; // Fraction
MSUB.QE[c], E[d], D[a], D[b] L, n (RRR1)
64 - (32 * 16L) --> 64
result = E[d] - ((D[a] * D[b][15:0]) << n);
E[c] = result[63:0]; // Multi-precision accumulator
31
c
28 27
d
24 23
02
H
18 17
n
16 15
b
12 11
a
8 7
63
H
0
31
c
28 27
d
24 23
1B
H
18 17
n
16 15
b
12 11
a
8 7
63
H
0
31
c
28 27
d
24 23
01
H
18 17
n
16 15
b
12 11
a
8 7
63
H
0
31
c
28 27
d
24 23
19
H
18 17
n
16 15
b
12 11
a
8 7
63
H
0

Infineon TriCore TC1.6P Specifications

General

Brand	Infineon
Model	TriCore TC1.6P
Category	Microcontrollers
Language	English