Infineon TriCore TC1.6P - Page 291

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-244
MSUB.QD[c], D[d], D[a], D[b] U, n (RRR1)
32 - (32 * 16U)Up --> 32
result = D[d] - (((D[a] * D[b][31:16]) << n) >> 16);
D[c] = result[31:0]; // Fraction
MSUB.QE[c], E[d], D[a], D[b] U, n (RRR1)
64 - (32 * 16U) --> 64
result = E[d] - ((D[a] * D[b][31:16]) << n);
E[c] = result[63:0]; // Multi-precision accumulator
MSUB.QD[c], D[d], D[a] L, D[b] L, n (RRR1)
32 - (16L * 16L) --> 32
sc = (D[a][15:0] == 8000
H
) AND (D[b][15:0] == 8000
H
) AND (n == 1);
mul_res = sc ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][15:0]) << n);
result = D[d] - mul_res;
D[c] = result[31:0]; // Fraction
MSUB.QE[c], E[d], D[a] L, D[b] L, n (RRR1)
64 - (16L * 16L) --> 64
sc = (D[a][15:0] == 8000
H
) AND (D[b][15:0] == 8000
H
) AND (n == 1);
mul_res = sc ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][15:0]) << n);
result = E[d] - (mul_res << 16);
E[c] = result[63:0]; // Multi-precision accumulator
MSUB.QD[c], D[d], D[a] U, D[b] U, n (RRR1)
32 - (16U * 16U) --> 32
sc = (D[a][31:16] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
mul_res = sc ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][31:16]) << n);
result = D[d] - mul_res;
31
c
28 27
d
24 23
00
H
18 17
n
16 15
b
12 11
a
8 7
63
H
0
31
c
28 27
d
24 23
18
H
18 17
n
16 15
b
12 11
a
8 7
63
H
0
31
c
28 27
d
24 23
05
H
18 17
n
16 15
b
12 11
a
8 7
63
H
0
31
c
28 27
d
24 23
1D
H
18 17
n
16 15
b
12 11
a
8 7
63
H
0
31
c
28 27
d
24 23
04
H
18 17
n
16 15
b
12 11
a
8 7
63
H
0